)]}'
{
  "commit": "031814cab0be05f2c9a46265ec348c8d0865e167",
  "tree": "0eda8777e68dddd78d5a9f9e0f38d02152ec812b",
  "parents": [
    "ab7404f3a431690566f233032fdadd5f8bacf4ea"
  ],
  "author": {
    "name": "Jiawei Shao",
    "email": "jiawei.shao@intel.com",
    "time": "Tue Apr 28 17:25:32 2026 -0700"
  },
  "committer": {
    "name": "dawn-scoped@luci-project-accounts.iam.gserviceaccount.com",
    "email": "dawn-scoped@luci-project-accounts.iam.gserviceaccount.com",
    "time": "Tue Apr 28 17:25:32 2026 -0700"
  },
  "message": "D3D12: Use `WaveLaneCountMax` as `SubgroupMaxSize` on Intel GPUs\n\nThis patch uses `mDeviceInfo.waveLaneCountMax` as `SubgroupMaxSize`\non Intel GPUs, where the reported `waveLaneCountMax` is reliable. On\nother vendors we still use 128 as `SubgroupMaxSize` temporarily as\nthe D3D12 value has not been considered reliable there.\n\nBug: 463721943\nChange-Id: I5e16239ad06abd1806ff8de19ffa8e7a51be0eb4\nReviewed-on: https://dawn-review.googlesource.com/c/dawn/+/305235\nReviewed-by: James Price \u003cjrprice@google.com\u003e\nCommit-Queue: Shao, Jiawei \u003cjiawei.shao@intel.com\u003e\nReviewed-by: Loko Kung \u003clokokung@google.com\u003e\nReviewed-by: Corentin Wallez \u003ccwallez@chromium.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b944df1001ae16fd94759101f071fa60a690c2a3",
      "old_mode": 33188,
      "old_path": "src/dawn/native/d3d12/PhysicalDeviceD3D12.cpp",
      "new_id": "c43b59b4dc2aa88ce4f5031d573485307133ecdd",
      "new_mode": 33188,
      "new_path": "src/dawn/native/d3d12/PhysicalDeviceD3D12.cpp"
    },
    {
      "type": "modify",
      "old_id": "a625faadda885d230a92c964d5fa2cf9384abcce",
      "old_mode": 33188,
      "old_path": "src/dawn/native/d3d12/PhysicalDeviceD3D12.h",
      "new_id": "2c5f58fbdb712be493e24171d8a785e63162b706",
      "new_mode": 33188,
      "new_path": "src/dawn/native/d3d12/PhysicalDeviceD3D12.h"
    }
  ]
}