Google Git
Sign in
dawn / dawn / 1efee19cc3ff7accd96be894b8b82b4cebdf295a / . / test / tint / expressions / bitcast / const / 128bit
tree: f6143fb82a728a3f81d471809afcba2e20a40cf3 [path history] [tgz]
  1. vec4f32-vec4f32.wgsl
  2. vec4f32-vec4f32.wgsl.expected.dxc.hlsl
  3. vec4f32-vec4f32.wgsl.expected.fxc.hlsl
  4. vec4f32-vec4f32.wgsl.expected.glsl
  5. vec4f32-vec4f32.wgsl.expected.ir.dxc.hlsl
  6. vec4f32-vec4f32.wgsl.expected.ir.fxc.hlsl
  7. vec4f32-vec4f32.wgsl.expected.ir.glsl
  8. vec4f32-vec4f32.wgsl.expected.ir.msl
  9. vec4f32-vec4f32.wgsl.expected.msl
  10. vec4f32-vec4f32.wgsl.expected.spvasm
  11. vec4f32-vec4f32.wgsl.expected.wgsl
  12. vec4f32-vec4i32.wgsl
  13. vec4f32-vec4i32.wgsl.expected.dxc.hlsl
  14. vec4f32-vec4i32.wgsl.expected.fxc.hlsl
  15. vec4f32-vec4i32.wgsl.expected.glsl
  16. vec4f32-vec4i32.wgsl.expected.ir.dxc.hlsl
  17. vec4f32-vec4i32.wgsl.expected.ir.fxc.hlsl
  18. vec4f32-vec4i32.wgsl.expected.ir.glsl
  19. vec4f32-vec4i32.wgsl.expected.ir.msl
  20. vec4f32-vec4i32.wgsl.expected.msl
  21. vec4f32-vec4i32.wgsl.expected.spvasm
  22. vec4f32-vec4i32.wgsl.expected.wgsl
  23. vec4f32-vec4u32.wgsl
  24. vec4f32-vec4u32.wgsl.expected.dxc.hlsl
  25. vec4f32-vec4u32.wgsl.expected.fxc.hlsl
  26. vec4f32-vec4u32.wgsl.expected.glsl
  27. vec4f32-vec4u32.wgsl.expected.ir.dxc.hlsl
  28. vec4f32-vec4u32.wgsl.expected.ir.fxc.hlsl
  29. vec4f32-vec4u32.wgsl.expected.ir.glsl
  30. vec4f32-vec4u32.wgsl.expected.ir.msl
  31. vec4f32-vec4u32.wgsl.expected.msl
  32. vec4f32-vec4u32.wgsl.expected.spvasm
  33. vec4f32-vec4u32.wgsl.expected.wgsl
  34. vec4i32-vec4f32.wgsl
  35. vec4i32-vec4f32.wgsl.expected.dxc.hlsl
  36. vec4i32-vec4f32.wgsl.expected.fxc.hlsl
  37. vec4i32-vec4f32.wgsl.expected.glsl
  38. vec4i32-vec4f32.wgsl.expected.ir.dxc.hlsl
  39. vec4i32-vec4f32.wgsl.expected.ir.fxc.hlsl
  40. vec4i32-vec4f32.wgsl.expected.ir.glsl
  41. vec4i32-vec4f32.wgsl.expected.ir.msl
  42. vec4i32-vec4f32.wgsl.expected.msl
  43. vec4i32-vec4f32.wgsl.expected.spvasm
  44. vec4i32-vec4f32.wgsl.expected.wgsl
  45. vec4i32-vec4i32.wgsl
  46. vec4i32-vec4i32.wgsl.expected.dxc.hlsl
  47. vec4i32-vec4i32.wgsl.expected.fxc.hlsl
  48. vec4i32-vec4i32.wgsl.expected.glsl
  49. vec4i32-vec4i32.wgsl.expected.ir.dxc.hlsl
  50. vec4i32-vec4i32.wgsl.expected.ir.fxc.hlsl
  51. vec4i32-vec4i32.wgsl.expected.ir.glsl
  52. vec4i32-vec4i32.wgsl.expected.ir.msl
  53. vec4i32-vec4i32.wgsl.expected.msl
  54. vec4i32-vec4i32.wgsl.expected.spvasm
  55. vec4i32-vec4i32.wgsl.expected.wgsl
  56. vec4i32-vec4u32.wgsl
  57. vec4i32-vec4u32.wgsl.expected.dxc.hlsl
  58. vec4i32-vec4u32.wgsl.expected.fxc.hlsl
  59. vec4i32-vec4u32.wgsl.expected.glsl
  60. vec4i32-vec4u32.wgsl.expected.ir.dxc.hlsl
  61. vec4i32-vec4u32.wgsl.expected.ir.fxc.hlsl
  62. vec4i32-vec4u32.wgsl.expected.ir.glsl
  63. vec4i32-vec4u32.wgsl.expected.ir.msl
  64. vec4i32-vec4u32.wgsl.expected.msl
  65. vec4i32-vec4u32.wgsl.expected.spvasm
  66. vec4i32-vec4u32.wgsl.expected.wgsl
  67. vec4u32-vec4f32.wgsl
  68. vec4u32-vec4f32.wgsl.expected.dxc.hlsl
  69. vec4u32-vec4f32.wgsl.expected.fxc.hlsl
  70. vec4u32-vec4f32.wgsl.expected.glsl
  71. vec4u32-vec4f32.wgsl.expected.ir.dxc.hlsl
  72. vec4u32-vec4f32.wgsl.expected.ir.fxc.hlsl
  73. vec4u32-vec4f32.wgsl.expected.ir.glsl
  74. vec4u32-vec4f32.wgsl.expected.ir.msl
  75. vec4u32-vec4f32.wgsl.expected.msl
  76. vec4u32-vec4f32.wgsl.expected.spvasm
  77. vec4u32-vec4f32.wgsl.expected.wgsl
  78. vec4u32-vec4i32.wgsl
  79. vec4u32-vec4i32.wgsl.expected.dxc.hlsl
  80. vec4u32-vec4i32.wgsl.expected.fxc.hlsl
  81. vec4u32-vec4i32.wgsl.expected.glsl
  82. vec4u32-vec4i32.wgsl.expected.ir.dxc.hlsl
  83. vec4u32-vec4i32.wgsl.expected.ir.fxc.hlsl
  84. vec4u32-vec4i32.wgsl.expected.ir.glsl
  85. vec4u32-vec4i32.wgsl.expected.ir.msl
  86. vec4u32-vec4i32.wgsl.expected.msl
  87. vec4u32-vec4i32.wgsl.expected.spvasm
  88. vec4u32-vec4i32.wgsl.expected.wgsl
  89. vec4u32-vec4u32.wgsl
  90. vec4u32-vec4u32.wgsl.expected.dxc.hlsl
  91. vec4u32-vec4u32.wgsl.expected.fxc.hlsl
  92. vec4u32-vec4u32.wgsl.expected.glsl
  93. vec4u32-vec4u32.wgsl.expected.ir.dxc.hlsl
  94. vec4u32-vec4u32.wgsl.expected.ir.fxc.hlsl
  95. vec4u32-vec4u32.wgsl.expected.ir.glsl
  96. vec4u32-vec4u32.wgsl.expected.ir.msl
  97. vec4u32-vec4u32.wgsl.expected.msl
  98. vec4u32-vec4u32.wgsl.expected.spvasm
  99. vec4u32-vec4u32.wgsl.expected.wgsl