)]}'
{
  "commit": "77f9a9aa5f7180958480de17680c61a84c006842",
  "tree": "492736777d13dca956f664a2c2300c9854143ebb",
  "parents": [
    "eb9ceabc4621cb624cc465e3875f54fdf8f29a7f"
  ],
  "author": {
    "name": "Hao Li",
    "email": "hao.x.li@intel.com",
    "time": "Fri Oct 02 13:05:54 2026 -0700"
  },
  "committer": {
    "name": "dawn-scoped@luci-project-accounts.iam.gserviceaccount.com",
    "email": "dawn-scoped@luci-project-accounts.iam.gserviceaccount.com",
    "time": "Fri Oct 02 13:05:54 2026 -0700"
  },
  "message": "Split buffer\u003c-\u003etexture copies to work around Intel row-pitch limitation\n\nIntel GPUs store a buffer\u003c-\u003etexture copy\u0027s bytes per row in an 18-bit\nhardware register (a row pitch of 262,144 bytes) and texels per row in\na separate 14-bit hardware register (a row width of 16,384 texels), so\na larger bytesPerRow silently overflows and corrupts the copy. Add a\nworkaround for Intel GPUs that splits affected buffer-to-texture and\ntexture-to-buffer copies on D3D11/D3D12/Vulkan into one command per row\nso the oversized bytes and texels is never handed to the driver.\n\nBug: 481934465\n\nChange-Id: Ib3e25be11f03d3f55205a3803dbbdb1817b9f7cb\nReviewed-on: https://dawn-review.googlesource.com/c/dawn/+/336315\nCommit-Queue: Corentin Wallez \u003ccwallez@chromium.org\u003e\nReviewed-by: Corentin Wallez \u003ccwallez@chromium.org\u003e\nReviewed-by: Loko Kung \u003clokokung@google.com\u003e\n",
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