[hlsl] Emit mip level 0 for storage textures
Bug: 42251045
Bug: 357896925
Change-Id: Icbf5f6f4f4b06ea337ad8fe6c2efe76366105f1c
Reviewed-on: https://dawn-review.googlesource.com/c/dawn/+/202363
Reviewed-by: dan sinclair <dsinclair@chromium.org>
Commit-Queue: Antonio Maiorano <amaiorano@google.com>
diff --git a/test/tint/builtins/gen/literal/textureLoad/e2b3a1.wgsl.expected.ir.dxc.hlsl b/test/tint/builtins/gen/literal/textureLoad/e2b3a1.wgsl.expected.ir.dxc.hlsl
index 334e6e8e..41f32d0 100644
--- a/test/tint/builtins/gen/literal/textureLoad/e2b3a1.wgsl.expected.ir.dxc.hlsl
+++ b/test/tint/builtins/gen/literal/textureLoad/e2b3a1.wgsl.expected.ir.dxc.hlsl
@@ -1,9 +1,19 @@
-SKIP: FAILED
-..\..\src\tint\utils\containers\slice.h:216 internal compiler error: TINT_ASSERT(i < Length())
-********************************************************************
-* The tint shader compiler has encountered an unexpected error. *
-* *
-* Please help us fix this issue by submitting a bug report at *
-* crbug.com/tint with the source program that triggered the bug. *
-********************************************************************
+RWByteAddressBuffer prevent_dce : register(u0);
+RWTexture2DArray<int4> arg_0 : register(u0, space1);
+int4 textureLoad_e2b3a1() {
+ RWTexture2DArray<int4> v = arg_0;
+ int2 v_1 = int2((1u).xx);
+ int4 res = int4(v.Load(int4(v_1, int(1), 0)));
+ return res;
+}
+
+void fragment_main() {
+ prevent_dce.Store4(0u, asuint(textureLoad_e2b3a1()));
+}
+
+[numthreads(1, 1, 1)]
+void compute_main() {
+ prevent_dce.Store4(0u, asuint(textureLoad_e2b3a1()));
+}
+
