[spirv-reader] Handle OpIAdd instructions
Bug: 42250952
Change-Id: I3fab3d79534ae8b5f5bf7a7e63e76eb467b24c58
Reviewed-on: https://dawn-review.googlesource.com/c/dawn/+/186963
Reviewed-by: Ben Clayton <bclayton@google.com>
diff --git a/src/tint/lang/spirv/reader/parser/binary_test.cc b/src/tint/lang/spirv/reader/parser/binary_test.cc
index eefea4e..bf5d71a 100644
--- a/src/tint/lang/spirv/reader/parser/binary_test.cc
+++ b/src/tint/lang/spirv/reader/parser/binary_test.cc
@@ -50,8 +50,12 @@
OpEntryPoint GLCompute %main "main"
OpExecutionMode %main LocalSize 1 1 1
%void = OpTypeVoid
+ %i32 = OpTypeInt 32 1
+ %u32 = OpTypeInt 32 0
%f16 = OpTypeFloat 16
%f32 = OpTypeFloat 32
+ %vec3i = OpTypeVector %i32 3
+ %vec4u = OpTypeVector %u32 4
%vec3h = OpTypeVector %f16 3
%vec4f = OpTypeVector %f32 4
%ep_type = OpTypeFunction %void
@@ -128,6 +132,28 @@
"vec4f",
"OpFMul",
"%5:vec4<f32> = mul %3, %4",
+ },
+
+ // OpIAdd
+ BinaryCase{
+ "i32",
+ "OpIAdd",
+ "%5:i32 = add %3, %4",
+ },
+ BinaryCase{
+ "u32",
+ "OpIAdd",
+ "%5:u32 = add %3, %4",
+ },
+ BinaryCase{
+ "vec3i",
+ "OpIAdd",
+ "%5:vec3<i32> = add %3, %4",
+ },
+ BinaryCase{
+ "vec4u",
+ "OpIAdd",
+ "%5:vec4<u32> = add %3, %4",
}),
PrintBuiltinCase);
diff --git a/src/tint/lang/spirv/reader/parser/parser.cc b/src/tint/lang/spirv/reader/parser/parser.cc
index d6c4f60..8fadddf 100644
--- a/src/tint/lang/spirv/reader/parser/parser.cc
+++ b/src/tint/lang/spirv/reader/parser/parser.cc
@@ -523,6 +523,9 @@
case spv::Op::OpFunctionCall:
EmitFunctionCall(inst);
break;
+ case spv::Op::OpIAdd:
+ EmitBinary(inst, core::BinaryOp::kAdd);
+ break;
case spv::Op::OpLoad:
Emit(b_.Load(Value(inst.GetSingleWordOperand(2))), inst.result_id());
break;
