Sign in
dawn
/
dawn
/
fa3f89b26b1bb003391d0baf5005c20e50e9b782
/
.
/
test
/
tint
/
expressions
/
bitcast
/
const
/
32bit
tree: 5ed26b9113320f6fdd70ae2b2b453ea22d6562f0 [
path history
]
[
tgz
]
f32-f32.wgsl
f32-f32.wgsl.expected.dxc.hlsl
f32-f32.wgsl.expected.fxc.hlsl
f32-f32.wgsl.expected.ir.dxc.hlsl
f32-f32.wgsl.expected.ir.fxc.hlsl
f32-f32.wgsl.expected.ir.glsl
f32-f32.wgsl.expected.ir.msl
f32-f32.wgsl.expected.msl
f32-f32.wgsl.expected.spvasm
f32-f32.wgsl.expected.wgsl
f32-i32.wgsl
f32-i32.wgsl.expected.dxc.hlsl
f32-i32.wgsl.expected.fxc.hlsl
f32-i32.wgsl.expected.ir.dxc.hlsl
f32-i32.wgsl.expected.ir.fxc.hlsl
f32-i32.wgsl.expected.ir.glsl
f32-i32.wgsl.expected.ir.msl
f32-i32.wgsl.expected.msl
f32-i32.wgsl.expected.spvasm
f32-i32.wgsl.expected.wgsl
f32-u32.wgsl
f32-u32.wgsl.expected.dxc.hlsl
f32-u32.wgsl.expected.fxc.hlsl
f32-u32.wgsl.expected.ir.dxc.hlsl
f32-u32.wgsl.expected.ir.fxc.hlsl
f32-u32.wgsl.expected.ir.glsl
f32-u32.wgsl.expected.ir.msl
f32-u32.wgsl.expected.msl
f32-u32.wgsl.expected.spvasm
f32-u32.wgsl.expected.wgsl
f32-vec2f16.wgsl
f32-vec2f16.wgsl.expected.dxc.hlsl
f32-vec2f16.wgsl.expected.fxc.hlsl
f32-vec2f16.wgsl.expected.ir.dxc.hlsl
f32-vec2f16.wgsl.expected.ir.fxc.hlsl
f32-vec2f16.wgsl.expected.ir.glsl
f32-vec2f16.wgsl.expected.ir.msl
f32-vec2f16.wgsl.expected.msl
f32-vec2f16.wgsl.expected.spvasm
f32-vec2f16.wgsl.expected.wgsl
i32-f32.wgsl
i32-f32.wgsl.expected.dxc.hlsl
i32-f32.wgsl.expected.fxc.hlsl
i32-f32.wgsl.expected.ir.dxc.hlsl
i32-f32.wgsl.expected.ir.fxc.hlsl
i32-f32.wgsl.expected.ir.glsl
i32-f32.wgsl.expected.ir.msl
i32-f32.wgsl.expected.msl
i32-f32.wgsl.expected.spvasm
i32-f32.wgsl.expected.wgsl
i32-i32.wgsl
i32-i32.wgsl.expected.dxc.hlsl
i32-i32.wgsl.expected.fxc.hlsl
i32-i32.wgsl.expected.ir.dxc.hlsl
i32-i32.wgsl.expected.ir.fxc.hlsl
i32-i32.wgsl.expected.ir.glsl
i32-i32.wgsl.expected.ir.msl
i32-i32.wgsl.expected.msl
i32-i32.wgsl.expected.spvasm
i32-i32.wgsl.expected.wgsl
i32-u32.wgsl
i32-u32.wgsl.expected.dxc.hlsl
i32-u32.wgsl.expected.fxc.hlsl
i32-u32.wgsl.expected.ir.dxc.hlsl
i32-u32.wgsl.expected.ir.fxc.hlsl
i32-u32.wgsl.expected.ir.glsl
i32-u32.wgsl.expected.ir.msl
i32-u32.wgsl.expected.msl
i32-u32.wgsl.expected.spvasm
i32-u32.wgsl.expected.wgsl
i32-vec2f16.wgsl
i32-vec2f16.wgsl.expected.dxc.hlsl
i32-vec2f16.wgsl.expected.fxc.hlsl
i32-vec2f16.wgsl.expected.ir.dxc.hlsl
i32-vec2f16.wgsl.expected.ir.fxc.hlsl
i32-vec2f16.wgsl.expected.ir.glsl
i32-vec2f16.wgsl.expected.ir.msl
i32-vec2f16.wgsl.expected.msl
i32-vec2f16.wgsl.expected.spvasm
i32-vec2f16.wgsl.expected.wgsl
i32min-u32.wgsl
i32min-u32.wgsl.expected.dxc.hlsl
i32min-u32.wgsl.expected.fxc.hlsl
i32min-u32.wgsl.expected.ir.dxc.hlsl
i32min-u32.wgsl.expected.ir.fxc.hlsl
i32min-u32.wgsl.expected.ir.glsl
i32min-u32.wgsl.expected.ir.msl
i32min-u32.wgsl.expected.msl
i32min-u32.wgsl.expected.spvasm
i32min-u32.wgsl.expected.wgsl
u32-f32.wgsl
u32-f32.wgsl.expected.dxc.hlsl
u32-f32.wgsl.expected.fxc.hlsl
u32-f32.wgsl.expected.ir.dxc.hlsl
u32-f32.wgsl.expected.ir.fxc.hlsl
u32-f32.wgsl.expected.ir.glsl
u32-f32.wgsl.expected.ir.msl
u32-f32.wgsl.expected.msl
u32-f32.wgsl.expected.spvasm
u32-f32.wgsl.expected.wgsl
u32-i32.wgsl
u32-i32.wgsl.expected.dxc.hlsl
u32-i32.wgsl.expected.fxc.hlsl
u32-i32.wgsl.expected.ir.dxc.hlsl
u32-i32.wgsl.expected.ir.fxc.hlsl
u32-i32.wgsl.expected.ir.glsl
u32-i32.wgsl.expected.ir.msl
u32-i32.wgsl.expected.msl
u32-i32.wgsl.expected.spvasm
u32-i32.wgsl.expected.wgsl
u32-u32.wgsl
u32-u32.wgsl.expected.dxc.hlsl
u32-u32.wgsl.expected.fxc.hlsl
u32-u32.wgsl.expected.ir.dxc.hlsl
u32-u32.wgsl.expected.ir.fxc.hlsl
u32-u32.wgsl.expected.ir.glsl
u32-u32.wgsl.expected.ir.msl
u32-u32.wgsl.expected.msl
u32-u32.wgsl.expected.spvasm
u32-u32.wgsl.expected.wgsl
u32-vec2f16.wgsl
u32-vec2f16.wgsl.expected.dxc.hlsl
u32-vec2f16.wgsl.expected.fxc.hlsl
u32-vec2f16.wgsl.expected.ir.dxc.hlsl
u32-vec2f16.wgsl.expected.ir.fxc.hlsl
u32-vec2f16.wgsl.expected.ir.glsl
u32-vec2f16.wgsl.expected.ir.msl
u32-vec2f16.wgsl.expected.msl
u32-vec2f16.wgsl.expected.spvasm
u32-vec2f16.wgsl.expected.wgsl
vec2f16-f32.wgsl
vec2f16-f32.wgsl.expected.dxc.hlsl
vec2f16-f32.wgsl.expected.fxc.hlsl
vec2f16-f32.wgsl.expected.ir.dxc.hlsl
vec2f16-f32.wgsl.expected.ir.fxc.hlsl
vec2f16-f32.wgsl.expected.ir.glsl
vec2f16-f32.wgsl.expected.ir.msl
vec2f16-f32.wgsl.expected.msl
vec2f16-f32.wgsl.expected.spvasm
vec2f16-f32.wgsl.expected.wgsl
vec2f16-i32.wgsl
vec2f16-i32.wgsl.expected.dxc.hlsl
vec2f16-i32.wgsl.expected.fxc.hlsl
vec2f16-i32.wgsl.expected.ir.dxc.hlsl
vec2f16-i32.wgsl.expected.ir.fxc.hlsl
vec2f16-i32.wgsl.expected.ir.glsl
vec2f16-i32.wgsl.expected.ir.msl
vec2f16-i32.wgsl.expected.msl
vec2f16-i32.wgsl.expected.spvasm
vec2f16-i32.wgsl.expected.wgsl
vec2f16-u32.wgsl
vec2f16-u32.wgsl.expected.dxc.hlsl
vec2f16-u32.wgsl.expected.fxc.hlsl
vec2f16-u32.wgsl.expected.ir.dxc.hlsl
vec2f16-u32.wgsl.expected.ir.fxc.hlsl
vec2f16-u32.wgsl.expected.ir.glsl
vec2f16-u32.wgsl.expected.ir.msl
vec2f16-u32.wgsl.expected.msl
vec2f16-u32.wgsl.expected.spvasm
vec2f16-u32.wgsl.expected.wgsl
vec2f16-vec2f16.wgsl
vec2f16-vec2f16.wgsl.expected.dxc.hlsl
vec2f16-vec2f16.wgsl.expected.fxc.hlsl
vec2f16-vec2f16.wgsl.expected.ir.dxc.hlsl
vec2f16-vec2f16.wgsl.expected.ir.fxc.hlsl
vec2f16-vec2f16.wgsl.expected.ir.glsl
vec2f16-vec2f16.wgsl.expected.ir.msl
vec2f16-vec2f16.wgsl.expected.msl
vec2f16-vec2f16.wgsl.expected.spvasm
vec2f16-vec2f16.wgsl.expected.wgsl