test/tint/builtins/gen/literal/sinh/69cce2.wgsl.expected.wgsl

enable f16;

@group(0) @binding(0) var<storage, read_write> prevent_dce : f16;

fn sinh_69cce2() -> f16 {
  var res : f16 = sinh(1.0h);
  return res;
}

@fragment
fn fragment_main() {
  prevent_dce = sinh_69cce2();
}

@compute @workgroup_size(1)
fn compute_main() {
  prevent_dce = sinh_69cce2();
}

struct VertexOutput {
  @builtin(position)
  pos : vec4<f32>,
  @location(0) @interpolate(flat)
  prevent_dce : f16,
}

@vertex
fn vertex_main() -> VertexOutput {
  var out : VertexOutput;
  out.pos = vec4<f32>();
  out.prevent_dce = sinh_69cce2();
  return out;
}