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/
dawn
/
b975919dfb45406ca17162e4d44c74a650caa679
/
.
/
test
/
tint
/
statements
/
compound_assign
/
vector
/
shift_left.wgsl.expected.dxc.hlsl
blob: f44e256577573508bca639b2df71c0e59c370ce4 [
file
]
RWByteAddressBuffer
v
:
register
(
u0
);
[
numthreads
(
1
,
1
,
1
)]
void
foo
()
{
v
.
Store4
(
0u
,
asuint
(
asint
((
asuint
(
asint
(
v
.
Load4
(
0u
)))
<<
((
2u
).
xxxx
&
(
31u
).
xxxx
)))));
}